Taiwan Semiconductor Manufacturing Co. officially introduced its N2 (2nm class) fabrication technology, its first node that will use all-around-the-gate field-effect transistors (GAAFET), today at its TSMC 2022 Technology Symposium. The new manufacturing process will now offer performance and power benefits, but when it comes to transistor density, it will barely impress in 2025 when it goes live.
As a completely new process technology platform, TSMC’s N2 brings two key innovations: nanosheet transistors (this is what TSMC calls its GAAFETs) and rear power rail which both serve the same objective to increase the performance characteristics per watt of the node. GAA nanosheet transistors feature channels surrounded by gates on all four sides, which reduces leakage; moreover, their channels can be widened to increase drive current and improve performance or narrowed to minimize power consumption and cost. To supply these nanosheet transistors with enough power and now waste some of it, TSMC’s N2 uses a back-end power supply, which the foundry considers one of the best solutions to combat resistances in the back-end. -of-line (BEOL).
Indeed, in terms of performance and power consumption, TSMC’s nanosheet-based N2 node can boast 10%-15% higher performance at the same power and complexity, as well as lower power consumption. 25% to 30% less energy at the same frequency. and transistor count compared to TSMC’s N3E. However, the new node only increases chip density by about 1.1 times compared to the N3E.
|N2 versus N3E||N3E versus N5||N3 versus N5||N5 versus N7|
|Improved speed at the same power||10%~15%||+18%||+10% ~ 15%||+15%|
|Power reduction at the same speed||-23% ~ -30%||-34%||-25% ~ -30%||-30%|
|HVM startup||S2 2025||Q2/Q3 2023||H2 2022||Q2 2022|
Overall, TSMC’s N3 offers all-around performance increases and power consumption reductions. But in terms of density, the new technology can hardly impress. For example, TSMC’s N3E node offers a 1.3X increase in chip density over N5, which is a substantial increase. For fairness, we should note that TSMC uses somewhat convoluted “chip density” metrics to describe transistor density on N3E and N2 in its papers released at its 2022 technology symposium. Chip density essentially describes a hypothetical chip composed of 50% logic circuits, 30% SRAM and 20% analog circuits. Modern designs are very SRAM intensive, but SRAM barely scales, as do analog circuits; therefore, an N2 chip with 50% non-scalable circuitry will demonstrate poor scalability compared to an N3E IC. If compared to the N3S, a version of N3 optimized for transistor density, the result might be even less impressive.
TSMC is positioning its N2 for various applications, including mobile SoCs, high-performance CPUs, and GPUs. Among the features of the N2 platform (in addition to the GAA nanosheet transistors and rear power rail), the world’s #1 foundry mentions “chip integration”, which likely implies that many applications who will use N2 will also use multi-chip packages to optimize performance and cost.
As noted, TSMC will begin high-volume chip manufacturing using its N2 node in the second half of 2025, so keeping in mind the length of contemporary semiconductor production runs, expect that commercial 2nm chips will not emerge on the market until the end of 2025 or instead. in 2026. Of course, before now and in 2026, TSMC will offer a variety of N3 (3nm class) nodes, but that’s another story.