In science lab wearing a virtual reality headset
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I attended the IEEE IEDM 2021 as well as the associated MRAM Forum in San Francisco. It was a hybrid event with only around 40% of the speakers in attendance (especially many speakers from Asia did not come due to COVID and made their presentations as recordings). Physical attendance at the conference was also down from previous years. This blog will explore some of the interesting storage and memory developments and opportunities presented during the plenary discussions of the MEI conference.
Kinam Kim of Samsung Electronics provided an overview of the development expectations for semiconductor products, including DRAM and NAND flash memory. The figure below shows his projections for the development of DRAM, including changes in cell transistor structure, cell capacity, and possibly 3D DRAM stacking.
History and planned developments of DRAM until 2030
IEEE MEI 2021 Plenary Lecture by Kinan Kim from Samsung
Samsung Electronics recently introduced several new DRAM architectures to meet increased memory demands to support machine learning workflows, including a) HBM-PIM (High Bandwidth Memory Based On In-Memory Processing), b) AX-DIMM (accelerated DIMM), and c) DRAM based on CXL (express link calculation). HBM-PIM can increase system performance gains up to 2.5 times, while simultaneously reducing power consumption by 70%.
AX-DIMM can increase the energy efficiency of AI accelerator systems by minimizing data traffic between processor and DRAM. Finally, CXL-DRAM can dramatically reduce system latency and speed up the processing of data center HPC workloads by providing memory capacity on the order of Tera-bits (Tb).
The figure below shows Samsung’s projections for NAND flash memory.
History and projected developments of the NAND flash until 2030
IEEE MEI 2021 Plenary Lecture by Kinan Kim from Samsung
Kim said the current NAND flash bit density is around 10 Gb / mm2 and the number of stacked layers is increasing to 170 (Fig. 8). Samsung Electronics expects that cost-effective manufacturing of V-NAND with over 1,000 stack layers can be achieved through next-generation process innovations and new materials. For the next generation of V-NAND, the HARC (High Aspect Ratio Contact) etching process and cell current in the VNAND architecture are critical. Stack height will be addressed with multiple stacking and new processes and materials are needed to improve NAND flash memory signals with smaller stacked cells.
The following figure shows Samsung’s projections for advancements in multi-bit cells, new materials and architectures, and better cell control.
NAND Flash trend display for higher bit levels, advancements in cell design, and better cell control
IEEE IEDM 2021 PLENARY SPEECH BY KINAN KIM FROM SAMSUNG
Innovations in control circuits, which will reduce the spread of Vt, and new materials for charge trap layers, are key innovations. To meet the I / O bandwidth requirements, which are expected to double every three years, increased efforts to address thermal effects are needed. A wafer bonding process, for example, which decouples the thermal budget from the process for memory cells and peripheral transistors is one way to accomplish this.
Michael Abrash of Facebook Reality labs Research gave a plenary talk on “Creating the future: augmented reality, the next human-machine interface”. He explored developments in Virtual Reality (VR) and Augmented Reality (AR), collectively referred to as XRs that are in use today and developments that could enable future more immersive experiences and replace devices such as smartphones. by wearable technologies, such as AR glasses.
Making such devices possible will require new sensor technology, software (including ways to map and understand this world that incorporate personal contextual information, including historical interactions with this mapped representational world), as well as new ones. ways to pack electronics with advanced low-power processing capabilities.
These advanced low-power, miniaturized packages will require innovations in hardware and software design, heterogeneous package integration, and miniaturization, as shown in the figure below. Note in particular the mention of memory-centric computing as part of the HW-SW co-design and eNVMs in the field of miniaturization to achieve comfortable and useful AR / VR devices.
Innovations needed to enable future portable AR / VR devices
IEEE MEI 2021 PLENARY CONFERENCE BY Michael Abrash from Facebook
Abrash mentioned the possible use of spintronics, 2D materials, carbon nanotubes (CNRTs, functional interconnects, hoses, and meta-materials) to enable higher system performance, lower unit power density, and a smaller physical volume to allow these future portable devices.
He also mentioned the need to develop new architectures and domain-oriented accelerations to support machine learning (ML) but also for particular applications such as avatar tracking and reconstruction, audio, tracking eye and electromyography with wearable sensors on users’ arms. Algorithmic optimization will be required for model compression, low precision computation, and optimization of the design supporting the platform.
Current AR / VR computer systems consume the most power in data transfers and memory access. Sensor-based computing and memory-centric computing approaches, such as in-memory computing, will be needed to address these bottlenecks. Additionally, closer physical coupling of logic with memories, logic with sensors and displays can help reduce data movement. He also mentioned the importance of using built-in non-volatile memories such as Spin Transform Random Access Magnetic Memories (STT-MRAM) to achieve power and area optimization, as these memories have high density. higher than SRAM and are non-volatile, allowing more low power states.
He spoke about advancements in image sensors which include the use of a hybrid memory hierarchy (including SRAM and eNVM, such as MRAM) in the ML-on-sensor compute architecture to enable higher density and lower power. 3DIC technologies, such as three-layer stacking, via silicon vias (TSV) and hybrid bonding at the wafer level, will enable this heterogeneous monolithic integration. The figure below shows a distributed multi-camera AR / VR multi-camera computer system with various features including the use of hybrid memory systems. The figure also shows the energy and communication requirements for the different compute / communication paths.
Advanced multi-camera computer system for AR / VR applications
IEEE MEI 2021 PLENARY CONFERENCE BY Michael Abrash from Facebook
At IEEE IEDM 2021, Samsung spoke about expected developments in DRAM and NAND technology through 2030 to enable advanced electronics. Facebook spoke about the requirements including in-memory computing and emerging memories such as MRAM to enable future comfortable portable AR / VR devices that will enable new ways of working and interacting with others and the world that we call home. surrounded.