What you will learn:
- The main design features of the new Tensilica ConnX DSPs.
- What features do DSPs offer?
- Language and library support.
Today’s automobiles incorporate dozens of on-board processors connected through multiple digital networks, controlling and enhancing the operation of nearly every system. But whether the target is vehicle-to-vehicle, vehicle-to-infrastructure, 5G communications, a high-resolution imaging radar sensor, or a lower-cost solid-state LiDAR, all can benefit from the flexibility of a software solution. . This flexibility can best be achieved by implementing parts of the signal processing chain using programmable processors.
The new Tensilica ConnX 110 and ConnX 120 digital signal processors (DSP) developed by Cadence aim to provide engineers with the flexibility and performance needed for radar, LiDAR and communication applications. They may include legacy support for 4G, LTE Advanced, LTE, WCDMA, HSPA+, Wi-Fi, and DVB.
“Radar and communications processing trends require solutions that do more processing in less time,” said David Glasco, vice president of research and development for Tensilica IP at Cadence. “Automotive radar requires high resolution multi-antenna systems with fast response.
“Similarly, 5G wireless communications require much higher data rates and lower latencies than previous generations. The Tensilica ConnX 110 and ConnX 120 DSPs meet these requirements by extending the already efficient processing capability of the ConnX DSPs and enhancing them with even more low-power, low-area complex fixed- and floating-point data processing capability.
DSP Details
ConnX DSPs do this through highly parallel vector engines and, with compatible architectures, provide an upgrade path to other members of the ConnX family when needed. Likewise, if processing needs to scale beyond that of a single DSP, the ConnX family can support multi-core solutions.
Depending on requirements, hardware blocks can be interfaced to Tensilica ConnX processors through dedicated custom interfaces under ConnX processor control or as initiators/responders through system bus interfaces or through shared memory.
ConnX processors, well suited for control code execution, are used to perform PHY application layer control in addition to digital signal processing. This opens the door to hardware savings opportunities and a broader scope of applications than a dedicated fixed hardware solution is likely to provide.
Tensilica ConnX DSPs offer pre-verified throttle instruction options. These options are included/excluded as checkboxes when defining a kernel, allowing efficient integration of this functionality into hardware, compiler, modeling tools, and verification scripts. With these features, designers can create a custom DSP without the significant development schedule impact that would normally be involved with a hardware design change.
The ConnX 110 128-bit DSP and ConnX 120 256-bit DSP feature an N-way programming model and are fully compatible with the higher performance ConnX B10 and B20 DSPs, sharing a common instruction set architecture for easy migration .
N-version programming, also known as multi-version programming, is a software engineering method or process in which multiple functionally equivalent programs are independently generated from the same initial specifications. The objective is to improve the reliability of software operation by integrating fault tolerance or redundancy.
TIE-related
Like the rest of the Tensilica DSP line, the ConnX 110 and ConnX 120 support the Tensilica Instruction Extension (TIE) language. TIE allows users to customize the instruction set, add specialized data types, and implement integrated interfaces between the DSP and external logic. Additionally, the new DSPs are supported by a comprehensive set of complex math library functions in the NatureDSP, Eigen, and Radar libraries. All ConnX DSPs are automotive ready with full ISO 26262 compliance to ASIL-D with FlexLock or ASIL-B.
The Tensilica ConnX 110 and 120 DSPs offer the following features and capabilities:
- Instruction set optimized for radar, LiDAR and communication applications.
- Rapid development with familiar C programming in an Eclipse-based IDE, plus optimized math libraries and sample applications with source.
- 128-bit (ConnX 110) and 256-bit (ConnX 120) SIMD performance for complex mathematical operations based on 8-, 16-, and 32-bit fixed-point and half-, standard-, and double-precision floating point.
- A common instruction set and simplified programming model, allowing code to be written once and used across different SIMD widths within the ConnX family.
- Architecture optimized for low memory footprint and low power signal processing.
- Optional easing operations for linear feedback shift, convolutional coding (a type of error-correcting code), single peak search, and dual peak search
- The ConnX 120 also offers Viterbi and Turbo decoders.
Tensilica ConnX DSPs come with a full set of software tools. The toolset includes a C/C++ compiler with automatic vectorization and instruction grouping to support the VLIW pipeline in the DSP. Also, the toolset includes linker, assembler, debugger, profiler, and graphical viewer. An instruction set simulator (ISS) allows users to quickly simulate and evaluate performance.
When working with large systems or long test vectors, the TurboXim simulator option achieves speeds that would be 40 to 80 times faster for efficient software development and functional verification. C-based Xtensa SystemC (XTSC) and Xtensa Modeling Protocol (XTMP) systems modeling are available for full-chip simulations. Pin-level XTSC provides co-simulation of SystemC and RTL-level offload accelerator blocks for fast and accurate simulations.
