AMD Introduces Adaptive 400 Gigabyte SmartNIC SOC to Hot Chips


After finalizing its acquisitions of FPGA vendor Xilinx (February 2022) and DPU vendor Pensando (May 2022), AMD yesterday introduced what it calls a 400 Gig adaptive smartNIC SOC to Hot Chips. It’s another contender in the increasingly cluttered and fuzzy smartNIC/DPU space where distinguishing between the two isn’t always easy.

Jaideep Dastidar

The motivation for these types of devices, presented by Jaideep Dastidar, who joined AMD from Xilinx, closely resembles presentations made by Nvidia, Intel and others in recent years. Host processors are overloaded with housework (networking, storage, security tasks). This is complicated by increasing performance and bandwidth demands, resource disaggregation, and the rise of software that defines everything.

Dastidar said:[The] reason to move to smartNICs and DPUs [is] it all started with the industry’s move towards software-defined networking, which quickly spread to software-defined storage, and before you knew it, you had everything software-defined. Meanwhile, the relentless march of speeds and streams continues, network bandwidths have rapidly increased by 25, 50, 100, 200 gig. And the level of virtualization has also expanded those where you have virtual machines and the unique digits (VM) have already reached 10s and with containerization you are dealing with thousands of virtual entities.

“All of this resulted in a situation where you had an overloaded CPU. So the CPU, instead of running multi-tenant applications, was taken up by running the data center infrastructure. So at the rescue came smartNICs and DPUs, as they help offload those workloads from the host CPU, and then the host CPU can focus on multi-tenant cloud applications again.

It is, now, a familiar message. It will be interesting to follow the evolution of the market. AMD is promoting its smartNIC as an efficient and flexible SOC that leverages fixed logic ASIC technology where applicable, more flexible programmable logic (FPGA) where applicable, and integrated processor cores. AMD, of course, positions itself as a strong supplier of all three types of technology (ASIC, FPGA and CPU/core).

Like others, AMD also integrates advanced security management into its system. The use cases are potentially quite varied, spanning network management, storage management, and security. CXL 2.0 support was notable.

“CXL is definitely a nascent technology. In type two devices, you can cache host memory, as well as device-attached memory that is accelerated. Right now with Programmable Logic, we just wanted to provide the flexibility that you can either connect the smartNIC as a traditional PCIe endpoint, but you can also explore use cases. From a CXL perspective, you kind of need a whole bunch of ecosystem support and so on, we’re just creating the capability – creating the core technology – so people can go and explore the different cases of ‘use that might work better as a CXL type two device,’ Dastidar said.

Using the slide above as a map, Dastidar gave AMD’s design tour: “We decided to take the traditional hardware-software co-design paradigm and extend it to hardware- software-programmable logic What you see in the figure (slide above) on the right, top, we apply ASIC logic where it works best: cryptographic offload, DMA offload, and even full data plane offload of the Then, as you go clockwise, we added ASIC logic adapters to programmable, where you start wanting to overlay customizations like custom header extensions Continuing clockwise you can also hot add or completely remove new throttle functions in the programmable logic.Then if you want to tilt the scale completely, we wanted the SOC to also perform a full offload of the custom data plane.

“Continuing clockwise. When you have programmable logic agents that need to interact with the embedded processing subsystem, we have programmable software-to-software adapter interfaces, so you can create consistent IO agents interacting with the embedded processor subsystem. Now the embedded processing subsystem has been sized to run the network control plane. If you notice, this is the first time we’ve mentioned the control plane. Meanwhile, the data plane is running full, either in ASIC logic, programmable logic, or a combination of the two,” he said.

About the telemetry functionality, Dastidar said that although the telemetry data is SOC-wide, the embedded processing subsystem is the “best place to gather all that telemetry data, synthesize it, and then upload them to the cloud management plan if they wish. ”

The SOC will be fabricated using TSMC’s 7nm process and will consist of functional blocks. While Dastidar presented a fair amount of material on features and supported functionality, it said little about what programming tools would be needed.

As shown in the slide above, AMD has mapped these design ideas into specific subsystems within the adaptive SOC. The host subsystem contains host connectivity and host domain acceleration. The network subsystem that contains network connectivity and network domain acceleration. The processing subsystem contains all the integrated processing cores.

Dastidar said, “Although it is shown here visually, I want you to think of the programmable logic element and the memory subsystem as ubiquitous on-chip resources with ubiquitous on-chip connectivity and access. This connectivity is further enhanced by the on-chip programmable network [which] allows movement of data from subsystem to subsystem, and any of the subsystems can access a common memory location if they so choose in terms of architecture.

Dastidar also went through each subsystem. Here is an excerpt from his description of the host subsystem.

“Host connectivity can be a single-host PCIe Gen 5 x16 connection to the smartNIC. Alternatively, it can be up to a quad-host 4x Gen five x4 connection to the smartNIC. Additionally, the controller supports CXL 2.0 and can support CXL type one, type two or type three devices. Now, as I mentioned earlier, PCIe controllers have been upgraded to the latest PCIe ECN security standards. For example , PCIe CMA (Component Measurement and Authentication), PCIe DOE (Device Object Exchange), PCIe IDE (Data Integrity and Encryption) and controllers also support TDX, which allows trusted virtual machines to communicate from confidentially with the terminal,” Dastidar said.

“The block in the middle is the composable DMA engine. It is a layered data transfer engine. Although it may continue to perform the traditional a la carte host offload [and] card-to-host data movement, it can also facilitate subsystem-to-subsystem data movement, and for host-to-card data, it can direct data to specific subsystems, whether the networking subsystem, programmable logic, or processing subsystem.

Slides showing the other three subsystems are included at the end of the article.

There is still a lot to digest and unpack. Dastidar did not say when the product might launch. It should be noted that the new smartNIC is based on Versal from Xilinx A PLUG (Adaptive Compute Acceleration Platform) smartNIC architecture. During the Q&A, Dastidar’s response to a question about distinguishing AMD’s new smartNIC from Pensando DPUs and Xilinx’s Versal smartNIC was a bit fuzzy.

“[We find] the combination of Xilinx smartNIC technology and Pensando DPU technology complement each other very well. Different data center customers have different engagement models. This broad portfolio offered by AMD now gives the customer the choice to commit to any of these models. You know that deployments in the data center are not homogeneous. There are cases where a customer may find the SOC-based adaptive smartNIC particularly attractive for a certain node in the data center, and Pensando’s DPU-based smartNIC is also very attractive. One common element we’ve noticed is this very strong emphasis on ease of use for the customer. From a cultural perspective, there is a very close match, both of an adaptive SOC in terms of how customers will interact with that SOC as well as with Pensando. There’s a lot of investment, a lot of effort to ensure that ease of use for the customer is the top priority.

AMD’s incorporation of Xilinx and Pensando is still in its infancy and it is perhaps unsurprising that the integration and harmonization of the product line is not yet settled. The smartNIC/DPU market is rapidly becoming more crowded and will be interesting to watch.


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